The present invention relates to readily testable integrated logic circuits, and more particularly to general-purpose integrated logic circuits of systematic structure having built-in flipflops, whose structural elements can be readily tested for correct operation.
While circuit integration technology has achieved remarkable progress over recent years, successfully realizing high-density integration of highly complex logic functions, detection of faulty elements has been made even more difficult by such constraints as circuit complexity, limitation on the number of input and output terminals and the impossibility of directly inspecting the internal structure. Programmable logic arrays (hereinafter abbreviated to PLAs) find increasingly extensive use as general-purpose integrated logic circuit elements because of their versatility and design facility. They so much the more require ready detection of faulty elements.
However, testing a large integrated logic circuit with respect to all possible input combinations would take an enormous length of time. More recently, there have emerged PLAs which, having built-in flipflops, permit composition of sequential circuits capable or more complex logical operations, and their testing is even more difficult. These integrated logic circuits are, therefore, so designed in advance as to allow ready examination of faulty elements whenever they arise.
Conventional circuit structures to facilitate testing of integrated logic circuits include one, as shown in the U.S. Pat. No. 3,958,110 entitled LOGIC ARRAY WITH TESTING CIRCUITRY issued to Hang et. al, in which outputs of specific signal lines (for example, the product term lines of an AND logic array) are received by a shift register whose content is led out. In another system known as the SCAN-PATH system, a group of flipflops which are present as internal memory elements for sequential circuit performance are interconnected to constitute the shift register for the testing purpose.
Both of these systems can give a large number of test outputs with the addition of a small number of observation terminals by taking out through a shift register the internal information of the circuit which is directly inaccessible, and thereby improve the testing capability. The SCAN-PATH system, in which the test input is inserted into the feedback loop by writing it into the shift register, can test even a sequential circuit performing complex logical operations merely as a combinational circuit.
These systems using a shift register, however, require advance preparation of the test inputs. Moreover, since information is written into or read out of the shift register in a scanning manner every time the test input is entered and the test result collected, not only extra time spent in testing but also it is impossible to perform dynamic testing of circuit functions under their real conditions.